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Re: ESP transform with RC5



*** Reply to note of 03/18/96 14:06                                            
>From the desk of:                                                              
   IBM Internal Use Only                                                       
SUBJECT: Re: ESP transform with RC5                                            
                                                                               
Re: absence of rotate on RISC processors                                       
                                                                               
Do you mean that an encryption algorithm must not be chosen which              
uses rotates because RISC processors don't have them, and everyone             
knows it?                                                                      
(dead horse - argued to death, well decided )                                  
                                                                               
This is not well decided.  Its invalid.  The RS6000 / PowerPC has              
single instruction variable count rotates which work in a single cycle.        
This cycle is likely to be overlapped with something else like I/O             
and disappear.                                                                 
                                                                               
Even other superscalar RISC processors which do not could still                
parallelize the sub-operations to some extent and overlap them                 
with I/O.                                                                      
                                                                               
The pentium and 486 have rotate instructions but they are many                 
cycle instructions. Presumably they don't use a barrel shifter.                
                                                                               
                                    regards,                                   
                                                                               
                                      Oscar Strohacker                         
                                                                               
                                                                               
Advisory Engineer/Scientist                                                    
Data Compression Systems Architecture                                          
IBM Microelectronics Division                                                  
11400 Burnet Road                                                              
Austin Texas 78758                                                             
                                                                               
o (512) 838-4077      f (512) 838-7004         Internet: stroh @ vnet.ibm.com