Re: speaking of keys

["Tarun Ahuja" <tarun.ahuja@cavium.com>]

The new generation of  crypto accelerators can do 40000+ RSA(yes forty
thousand and that's not a typo) operations/second using CRT.
You can get the details of the products by clicking on the following link.
http://www.cavium.com/Table.html

-Tarun

----- Original Message -----
From: "Joseph J. Tardo" <tardo@acm.org>
To: "Derrell Piper" <ddp@electric-loft.org>; "Paul Koning"
<pkoning@equallogic.com>
Cc: <ipsec@lists.tislabs.com>
Sent: Wednesday, December 11, 2002 9:46 PM
Subject: Re: speaking of keys


> The Broadcom chips indeed do native 2048-bit modulo arithmetic.
>
> Note that speed and cost are coming down not only for hardware (from
> multiple vendors) but also for software (e.g., tailored assembly code for
> the P4 and Itanium processors said to be capable of 800 RSA
> Signatures/second using CRT).
>
> At 11:32 AM 12/11/02 -0800, Derrell Piper wrote:
> >I mistyped that, I meant >1024 bits and I was specifically thinking
> >about the Hi/fn 6500.  I knew the Broadcom chips could do better, but I
> >wasn't sure what the limits were...  2048 seems to be pretty common now.
> >
> >Derrell
> >
> >On Wednesday, December 11, 2002, at 09:56 AM, Paul Koning wrote:
> >
> >>>>>>> "Derrell" == Derrell Piper <ddp@electric-loft.org> writes:
> >>
> >>  Derrell> What's the current state-of-the-art for COTS hardware
> >>  Derrell> accelerators?  It was the case a few years back that many
> >>  Derrell> public-key chips didn't do 1024 bit DH groups.  What's the
> >>  Derrell> story today?  Do we care?
> >>
> >> I don't remember ever seeing an accelerator with a limit less than
> >> 1024 bits in recent years (since IPsec).  The only other case that
> >> comes to mind is Rivest's research prototype bignum ALU chip, 512 bits
> >> wide, early 1980s.
> >>
> >>       paul
> >>
> >
> >